74HC160 Synchronous Decade Counter
High-speed Si-gate CMOS device with internal look-ahead carry
- Compatibility: Pin compatible with low power Schottky TTL (LSTTL)
- Compliance: JEDEC standard no. 7A
- Operation: Synchronous presettable decade counters
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Features:
- Synchronous counting and loading
- Two count enable inputs for n-bit cascading
- Positive-edge triggered clock
- Asynchronous reset
The 74HC160 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage.
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Specifications:
- Propagation delay (tPHL) CP to Qn: 19 ns
- Propagation delay (tPHL) CP to TC: 21 ns
- Propagation delay (tPHL) MR to Qn: 21 ns
- Propagation delay (tPHL) MR to TC: 21 ns
- Propagation delay (tPHL) CET to TC: 14 ns
- Propagation delay (tPLH) CP to Qn: 19 ns
- Propagation delay (tPLH) CP to TC: 21 ns
- Propagation delay (tPLH) CET to TC: 14 ns
- Maximum clock frequency (fmax): 61 MHz
- Input capacitance (C1): 3.5 pF
- Power dissipation capacitance per package (CPD): 3.9 pF
Related Document: 74HC160 IC Datasheet
* Images are for illustration only; actual product may vary.