74HC160 Synchronous Decade Counters
High-speed CMOS counters with synchronous operation and internal carry
- Package Type: 16-pin PDIP
- Compliance: JEDEC standard no. 7A
- Output Capability: Standard
- IC Category: MSI
- Input Capacitance: 3.5 pF
- Power Dissipation Capacitance: 39 pF
Top Features:
- Synchronous counting and loading
- Two count enable inputs for cascading
- Positive-edge triggered clock
- Asynchronous reset
The 74HC160 are synchronous preset table decade counters with an internal look-ahead carry, designed for high-speed counting. Synchronous operation is achieved by clocking all flip-flops simultaneously at the positive-going edge of the clock (CP).
These counters can preset the outputs (Q0 to Q3) to a HIGH or LOW level. The counting action is disabled with a LOW level at the parallel enable input (PE). Data at the data inputs (D0 to D3) is then loaded into the counter on the positive-going edge of the clock.
Master reset input (MR) sets all outputs of the flip-flops to LOW level asynchronously. The look-ahead carry simplifies serial cascading. Both count enable inputs (CEP and CET) must be high to count, with CET forwarded to enable the terminal count output (TC).
The counters have a maximum clock frequency of 61 MHz, determined by propagation delays and set-up time. Refer to the datasheet for detailed specifications.
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