74LS73 Dual J-K Flip-Flop
Two independent J-K flip-flops with individual inputs and positive pulse-triggered operation.
- Supply Voltage: 4.5 - 5.25V
- Operating Temperature: 0°C - 70°C
- Output Current (High): -0.4 mA
- Output Current (Low): 8 mA
Top Features:
- Two independent flip-flops
- Positive pulse-triggered operation
- Negative-edge triggered
- Clear input overrides clock and data
The 74LS73 contains two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. It operates as a positive pulse-triggered flip-flop where data is loaded into the master on the high clock and transferred to the slave on the high-to-low transition. The J and K inputs must be stable while the clock is high for proper operation.
Additionally, the 74LS73 is characterized for operation from 0°C to 70°C. The negative-edge-triggered flip-flops require the J and K inputs to be stable one setup time before the high-to-low clock transition to ensure predictable operation. When the clear input is low, it overrides the clock and data inputs, setting the Q output low and the output high.
For more detailed information, refer to the related document: 74LS73 SMD Data Sheet.
Images are for illustration only; actual product may vary.