74HC73 Dual JK Flip-Flop with Reset IC (7473 IC)
A high-speed Si-gate CMOS device with dual negative-edge triggered JK flip-flop
- Supply Voltage: -0.5 to +7.0V
- Input diode current: +20mA
- Output diode current: +20mA
- Output source or sink current: +25mA
- GND current: +50mA
- Storage temperature: -65°C to +150°C
- Package Includes: 1 X 74HC73 Dual JK Flip-Flop with Reset IC (7473 IC) DIP-14 Package
Top Features:
- Low-power dissipation
- Complies with JEDEC standard no. 7A
- ESD protection: HBM EIA/JESD22-A114-B exceeds 2000V
- Multiple package options
The 74HC73 is a high-speed Si-gate CMOS device that is pin compatible with low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. This dual negative-edge triggered JK flip-flop features individual J, K, clock (nCP), and reset (nR) inputs, along with complementary nQ and nQ outputs. The J and K inputs need to be stable one set-up time before the HIGH-to-LOW clock transition for predictable operation. The reset (nR) is an asynchronous active LOW input that overrides the clock and data inputs when LOW, forcing the nQ output LOW and the nQ output HIGH. The Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Specified from -40°C to +80°C and from -40°C to +125°C, the 74HC73 is a versatile component suitable for a range of temperature conditions.
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