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74HC573 High Speed Octal D-Type Latches
Advanced silicon-gate P-well CMOS technology for high noise immunity and low power consumption.
- Supply Voltage: VCC - 0.5 to +7.0V
- Input Voltage: -1.5V to VCC + 1.5V
- Output Voltage: -0.5 to VCC + 0.5V
- Clamp Diode Current (IIK, IOK): ±20 mA
- DC Output Current, per pin (IOUT): ±35 mA
- DC VCC or GND Current, per pin (ICC): ±70 mA
- Storage Temperature Range (TSTG): -65°C to +150°C
- Power Dissipation (PD): 600 mW (S.O. Package only)
Features:
- Typical propagation delay: 18 ns
- Wide operating voltage range: 2 to 6 volts
- Low input current: 1 µA maximum
- Low quiescent current: 80 µA maximum
The 74HC573 latches are ideal for interfacing with bus lines in a bus organized system. The LATCH ENABLE(LE) input controls the Q outputs based on the D inputs. The OUTPUT CONTROL OC input puts all outputs in a HIGH impedance state when a HIGH logic level is applied. These latches are compatible with bus-oriented systems and have an output drive capability of 15 LS-TTL loads. The 74HC logic family is compatible with the standard 74LS logic family.
All inputs are protected from static discharge damage by internal diode clamps to VCC and ground.
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Images are for illustration only; actual product may vary.