74HC161 Presettable Synchronous 4-bit Binary Counter IC
A versatile synchronous counter with preset capability and internal carry look-ahead.
- Supply voltage: 2.0 V to 6.0 V
- Input clamp current: - to +20 mA
- Output clamp current: - to +20 mA
- Output current: - to +25 mA
- Supply current: - to 50 mA
- Ground current: -50 mA
- Storage temperature: -65°C to +150°C
- Total power dissipation: - to 500 mW
- Package Includes: 1 X 74HC161 Presettable Synchronous 4-bit Binary Counter IC (74161 IC) DIP-16 Package
Features:
- Wide supply voltage range (2.0 V to 6.0 V)
- Low power dissipation
- High noise immunity
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CPto TC propagation delay and CEP to CP set-up time.
Specified from -40 °C to +85 °C and -40 °C to +125 °C.
* Images are for illustration only; actual product may vary.