74HC138 Decoder
Advanced silicon-gate CMOS technology for memory address decoding or data routing.
- Supply Voltage: 2V–6V
- Input Voltage: -0.5V to VDD + 0.5V
- Output Voltage: -0.5V to VCC + 0.5V
- Clamp Diode Current (IIK, IOK): ±20 mA
- Output Current, per pin (IOUT): ±25 mA
- VCC or GND Current, per pin (ICC): ±50 mA
- Storage Temperature Range (TSTG): -65°C to +150°C
- Power Dissipation (PD): 600 mW (S.O. Package only)
- Lead Temperature (TL): 260°C (Soldering 10 seconds)
Features:
- Typical propagation delay: 20 ns
- Wide power supply range: 2V–6V
- Low quiescent current: 80 µA maximum (74HC Series)
- Low input current: 1 µA maximum
The 74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The 74HC138 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of decoders. The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Related Document: 74HC138 IC Datasheet
* Images are for illustration only; actual product may vary.