74HC109 Dual Positive Edge-Triggered JK Flip-Flop
Dual flip-flop with individual nJ and nK inputs, CMOS, and TTL level compatibility
- Supply Voltage: -0.5 - 7 V
- Input Clamping Current: ±20 mA
- Output Clamping Current: ±20 mA
- Output Current: ±25 mA
- Supply Current: 50 mA
- Ground Current: -50 mA
- Storage Temperature: -65 - 150 °C
- Total Power Dissipation: 500 mW
Top Features:
- CMOS and TTL level inputs
- J and K inputs for D-type flip-flop
- Toggle or "do nothing" mode
- ESD protection exceeding 2000V
The 74HC109 is a dual positive edge-triggered JK flip-flop with individual nJ and nK inputs as well as clock inputs, set and reset inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active Low inputs and operate independently of the clock input.
The nJ and nK inputs control the state changes of the flip-flops and must be stable one set-up time prior to the Low-to-High clock transition for predictable operation.
The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs. It includes clamp diodes and enables the use of current limiting resistors to interface inputs to voltages exceeding VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Specified in compliance with JEDEC standard no. 7A, the 74HC109 comes with multiple package options and is specified for operation from -40 °C to +85 °C and from -40 °C to +125 °C.
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Images are for illustration only; actual product may vary.